About

My first name dances to the tune of ‘vaa-SEE-lee-aws’ while my surname is a breeze – just ‘CLEM-iss’

As for my day job, I am a Lecturer (Assistant Professor in US lingo) at Queen Mary University of London in the School of Electronic Engineering and Computer Science.

My latest research involves taking those highbrow formalisations (whether they happen to be my own brainchildren or someone else’s prodigies) on a robust reality check. The aim is to keep them firmly rooted and ensure they don’t become too comfortable in the territory of theoretical daydreams. We’re talking about some hands-on fuzz-testing and real-world validation, right there in the domain of the big, bad machines. It's much like daring to cook a gourmet meal from a celebrity chef's "gastronomic hypothesis" for the very first time in your own kitchen! The results can be as unexpectedly delightful as they are humorously catastrophic. Throughout this expedition, I'm the curious collector of both triumphs and, well, let's call them 'epicurean experiments'. The recipes I've been cooking up include languages for graphical shaders, the intriguing world of weak memory semantics, and exploring models of RDMA on TSO Architectures.

In the archives of my research odyssey, I once tiptoed into the quirky kingdom of network verification, attempting to tame and give Software-Defined Networks a thorough 'Are you really as defined as you claim?' interrogation.

Projects

Validating Memory Persistency Models

an empirical adventure through the wilds of persistency semantics

Formalising Structured Control-Flow in SPIR-V

a lighthearted success with lightweight formal methods

Navigating the Wonderland of SDNs

ensuring correctness in the realm of Software-Defined Networks with model-checking

Publications

A. F. Donaldson. Taking Back Control in an Intermediate Representation for GPU Computing. Proc. ACM on Programming Languages 7 (POPL), 2023.

PDF

Towards Model Checking Real-World Software-Defined Networks. In Int. Conf. on Computer Aided Verification (CAV), 2020.

PDF Extended Version

Model Checking Software-Defined Networks with Flow Entries that Time Out. In Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design (FMCAD), 2020.

PDF Extended Version

A Tag Cloud of my publications

Teaching

Professional Engagement

Highlights from my recent professional involvement

  • Joined the party at The Future of Weak Memory 2024 workshop during POPL '24, sharing perspectives on navigating the challenges of weak memory persistency semantics validation. Explore the presentation slides and position paper here for more details.
  • Back in 2023, I had a blast at Schloss Dagstuhl, casually chatting about my exploration with a memory bus intercept gadget in validating weak memory persistency semantics. Check out the slides for a brief glimpse into the discussion! Access them right here.